Embedded & VLSI
Cauvery Softwarehas different engagement models, from consulting to Final delivery of chips. We provide consulting services in all ASIC Design domains.
Teledyne Systems team expertise in Design Implementation encompasses flows/methodologies from front-end to the back-end. The core-skills include RTL Design, Verification, RTL Synthesis, Timing Analysis, DFT, Formal Verification, Physical Design Closure (Floorplanning, Clock Tree Synthesis, P&R, Timing, Noise, Power & IR-Drop/Electromigration Analysis and Physical Verification).
Design
- Architectural Design Implementation
- Spec Development RTL, Implementation (SV, Verilog, VHDL,) and Simulation.
- Synthesis
- Timing
- Verification
Full Custom Activity (AMS )
- Full Custom Activity (AMS )
- Custom layout and Physical Verification
- Extraction
- Characterization, Spice Simulation
- Different models / View gereration
Implementation
- Synthesis / STA
- Physical Design
- Floorplan
- Clock distribution (CTS, HTree etc) and analysis
- Scan restitching (check formatting matches with remaining data)
- Place & Route
- Timing closure
- DFM
- Physical verification (DRC/LVS)
Verification
- Chip and System level verification
- Verification flow and Methodologies
- Set up Verification environment, Testbenches and Test Plan